The SOC / ASIC physical design engineer-backend, you will be collaborating with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge IC / SOCs for customers on Earth and beyond
RESPONSIBILITIES :
- Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power / ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop / improve physical design methodologies and automation scripts for various implementation steps
- Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL / design tradeoffs
- Resolve design / timing / congestion and flow issues, identify potential solutions and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
BASIC QUALIFICATIONS :
Bachelor’s degree in electrical engineering, computer engineering or computer science3+ years of ASIC and / or physical design flow development experience (internship and collegiate extracurricular engineering project experience qualifies)Automotive electronic device experienceVLSI design tools working level experienceExcellent oral and written communication skills